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this is information on a product in full production. september 2013 docid7791 rev 7 1/19 l9823 octal low-side driver for bulb, resistive and inductive loads with serial input control, outp ut protection and diagnostic datasheet - production data features ? outputs current capability up to 0.5 a ? cascadable spi control for outputs ? reset function with reset signal or undervoltage at v dd ? programmable intrinsic output voltage clamping at typ. 50 v for inductive switching ? overcurrent shutdown with latch-off for every write cycle (sfpd = low) ? independent thermal shutdown of outputs (soa protection) ? output status data ava ilable on the spi using 8-bit i/o protocol up to 3.0 mhz ? low standby current with reset = low (typ. 35 a @ vdd) ? open load detection (outputs off) ? single v dd logic supply ? high ems immunity and low eme (controlled output slopes) ? full functionality of th e remaining device at negative voltage drop on outputs (-1.5 v or -3.0 a) ? output mode programmable for sustained current limit or shutdown description l9823 is a octal low-side driver circuit, dedicated for automotive applications. output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. chip select and cascadable serial 8-bit interface for outputs control and diagnostic data transfer. '!0'03 so24 table 1. device summary order code package packing l9823 so24 tube E-L9823 so24 tube www.st.com
contents l9823 2/19 docid7791 rev 7 contents 1 block diagram and pins descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 power outputs characteristics for flyback current, outputs short circuit protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 output stages control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
docid7791 rev 7 3/19 l9823 list of tables 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. outputs control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. diagnostic for outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
list of figures l9823 4/19 docid7791 rev 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. output control register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. timing of the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. pulse diagram to read the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. structure of the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. typical application circuit diagram for the l9823 circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. so24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
docid7791 rev 7 5/19 l9823 block diagram and pins description 18 1 block diagram and pins description 1.1 block diagram figure 1. block diagram 1.2 pins description figure 2. pins connection (top view) $iag 1 #3" 3) 3# ,+ 3/ /54 /54 /5 4 /5 4 /54 /54 /54 /54 '. $ $iag $iag 2eset 1 #( /4 $iag 1 1 1 $ia g 1 #( #( #( #( $iag 1 $iag 1 $iag 1 1 #( $iag 2eset 3hift2egister /utput,atch 30) )nterface 2eset 5ndervol tage 2%3%4 1 1 1 1 1 1 $i ag $i ag $i ag $i ag $i ag $iag ) /, /ver 4emperature $etect 'ate #ontrol /, #( #( 3&0$ 6 $' $ia g $$ ) 3#" '!0'03 /54 /54 3#,+ 3) '.$ '.$ '.$ '.$ 3/ 6$$ '.$ '.$ '.$ '.$ .# 2%3%4 /54 /54 #3" 3&0$ /54 /54 /54 /54 '!0'03
block diagram and pins description l9823 6/19 docid7791 rev 7 table 2. pins description n# pin description 1 out7 output 7 2 out6 output 6 3sclk the system clock pin (sclk) clocks the internal shift registers of the l9823. the serial input pin (si) accepts data into the input shift register on the falling edge of the sclk signal while the serial output pin (so) shifts data informati on out of the shift regist er on the rising edge of the sclk signal. false clocking of the shift regi ster must be avoided to guarantee validity of data. it is essential that the sclk pin be in a logic low state whenever chip select bar pin (csb) makes any transition. for this reason, it is recommended though not necessary, that the sclk pin be kept in a low logic state as lo ng as the device is not accessed (csb in logic high state). when csb is in a logic high state, any signal at the sclk and si pin is ignored and so is tri-stated (high-impedance). 4si this pin is for the input of serial instruction data. si information is read in on the falling edge of sclk. a logic high state present on this pin when the sclk signal rises will program a specific output off, and in turn, turns off th e specific output on the rising edge of the csb signal. conversely, a logic low state present on the si pin will program the output on, and in turn, turns on the specific output on the rising edge of the csb signal. to program the eight outputs of the l9823 on or off, an eight bit se rial stream of data is required to be entered into the si pin starting with output 7, followed by output 6, output 5, etc., to output 0. for each rise of the sclk signal, with csb held in a logic low state, a databyte instruction (on or off) is loaded into the shift register per the dat abyte si state. the shift register is full after eight bits of information have been entered. to pr eserve data integrity, care should be taken to not transition si as sc lk transitions from a low-to-high logic state. 5gndgnd 6gndgnd 7gndgnd 8gndgnd 9so the serial output (so) pin is the tri-stateabl e output from the shift register. the so pin remains in a high impedance state until the csb pin goes to a logic low state. the so data reports the drain status, either high or low. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sc lk. when an output is of f and not faulted, the corresponding so databyte is a high state. when so an output is on, and there is no fault, the corresponding databyte on the so pin will be a low logic state. the si / so shifting of data follows a first-in-first-out pr otocol with both input and outpu t words transferring the most significant bit (msb) first. the so pin is not affected by the status of the reset pin. 10 csb the system mcu selects the l9823 to be comm unicated with through the use of the csb pin. whenever the pin is in a logic low state, dat a can be transferred from the mcu to the l9823 and vise versa. clocked-in data from the mcu is transferred from the l9823 shift register and latched into the power outputs on the rising edge of the csb signal. on the falling edge of the csb signal, drain status information is transfe rred from the power outputs and loaded into the device's shift register. the csb pin also controls the output driver of the serial output pin. whenever the csb pin goes to a logic low state, the so pin output driver is enabled allowing information to be transferred from the l9823 to the mcu. to avoid any spurious data, it is essential that the high-to-low tr ansition of the csb signal occur only when sclk is in a logic low state. 11 out5 output 5 12 out4 output 4 13 out3 output 3
docid7791 rev 7 7/19 l9823 block diagram and pins description 18 14 out2 output 2 15 sfpd the short fault protect disable (sfpd) pin is us ed to disable the overcurrent latch-off. this feature allows control of incandescent loads where in-rush currents exceed the device's analog current limits. essentially the sfpd pin determines whether the l9823 output(s) will instantly shutdown upon sensing an output short or remain on in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. if the sfpd pin is tied to v dd the l9823 output(s) will remain on in a current limited mode of operation upon encountering a load short to supply. if the sfpd pin is grounded, a short circuit will immediately shutdown only the output affected. other outputs not having a fault condition will operate normally. 16 vdd vdd 17 gnd gnd 18 gnd gnd 19 gnd gnd 20 gnd gnd 21 n.c. not connected 22 reset the reset pin is active low and used to clear the spi shift register and in doing so sets all output switches off. with th e device in a system with an mcu; upon initial system power up, the mcu holds the reset pin of the device in a logic low state ensuring all outputs to be off until the vdd pin voltages are adequate for pred ictable operation. after the l9823 is reset, the mcu is ready to assert system control with all output switches initia lly off. the reset pin is active low and has an internal pull-down incorporated to ensure operational predictability should the external pull-down of the mcu open circuit. the internal pull-up is to afford safe and easy interfacing to the mcu. the reset pi n of the l9823 should be pulled to a logic low state for a duration of at least 160ns to ensure reliable reset. 23 out1 output 1 24 out0 output 0 table 2. pins description (continued) n# pin description
electrical specifications l9823 8/19 docid7791 rev 7 2 electrical specifications 2.1 absolute maximum ratings for voltages and currents applied externally to the device. exceeding limits may cause damage to the device. 2.2 thermal data table 3. absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3 to 7 v inputs and data lines (csb, sclk, si, reset, sfpd, so) v in voltage (csb, sclk, si, reset, sfpd) -0.3 to 7 v sdo voltage (so) -0.3 to v dd +0.3 v i in protection diodes current (1) t ? 1ms 1. all inputs are protected against esd according to mil 883c; tested with hbm c = 100 pf, r = 1500 ? at ? 2kv. it corresponds to a dissipated energy e ? 0.2mj (data available upon request). -20 to 20 (1) ma outputs (out0 to out7) v out cont continuous output voltage -1.5 to 45 v v out cont continuous output current -3 to i out lim a i out peak output current -10 (2) to 2 2. transient pulses in accordance to din40839 part 1, 3 and iso 7637 part 1, 3. a e outclamp output clamp energy (3) 3. max. output clamp energy at t j = 150c, using single non-repetitive pulse of 500 ma 50 mj i out lim output current (self limit) 2 a table 4. thermal data symbol parameter value unit thermal shutdown t lim thermal shutdown threshold 155 (min.), 180 (typ.) c thermal resistance (junction-to-lead) r thjl-one single output (junction lead) 25 (max.) c/w r thjl-all all outputs (junction lead) 20 (max.) c/w t stg storage temperature -55 to 150 c
docid7791 rev 7 9/19 l9823 electrical specifications 18 2.3 electrical characteristics 4.5 v ? v dd ? 5.5 v; -40 c ? t j ? 150 c; unless otherwise specified. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit supply voltage i ddstb i ddleak standby current leakage current reset = low and / or v ddres >v dd > 0.5v v dd < 0.5v -35 <1 70 10 a i ddopm operating mode i out0 to 7 = 500 ma spi - sclk = 3 mhz csb = low so no load -- 6ma ? i dd rev ? i dd during reverse output current i out rev = -2.5 a - - 10 ma v dd res undervoltage reset reset of all registers and disable of all outputs 2.5 - 3.95 v inputs (csb, sclk, si, reset, sfpd) v inl low level - -0.3 - 0.2v dd v v inh high level - 0.7v dd - v dd +0. 3 v v hyst hysteresis voltage - 0.5 1.2 0.5 v dd v i in input current v in = v dd -10 - 10 a r in pull-up resistance (csb, si) pull-down resistance (sfpd, reset, sclk) - 50 - 250 k ? c in input capacitance - - - 10 pf serial data outputs v soh high output level i so = -4 ma v dd -0.4 - v v sol low output level i so = 3.2 ma - - 0.4 v i sol tristate leakage current csb = high; 0 v ? v so ? v dd -10 - 10 a c so output capacitance f so = 300 khz, 0 v ? v so ? v dd --20pf outputs out 0 to 7 i outl0 - 7 leakage current outx = off; v outx = 16v; v dd ? v dd res and / or reset = low tj ? 85c -10 <1 ? a 10 a v out clamp output clamp voltage 2ma ? i out clamp ? i out lim i out test = 20ma with correlation 45 - 60 v r dson on resistance out 0 ... 7 i out = 500ma;t j = +150c t j = +25c - 1 0.8 1.5 1.25 ?
electrical specifications l9823 10/19 docid7791 rev 7 c out output capacitance v out = 16 v; f = 1 mhz - - 300 pf outputs short circuit protection i scb overcurrent shutoff threshold sfpd = low, v out ? v dg 0.5 1.6 2.5 a i out lim short circuit current limitation - 0.5 1.6 2.5 a t dly scb short circuit shutdown delay sfpd = low, v out ? v dg csb = 50% to i out ? 1/2 i out lim 70 150 250 s diagnostics v dg diagnostic threshold voltage - 0.5 v dd 0.55 v dd 0.6 v dd v i out ol open load detection sink current v out = v dg output programmed off 30 60 100 a t dly sfpd diagnostic detection filter time sfpd = low, v out ? v dg csb = 50% to valid data at so 70 150 250 s outputs timing t don turn-on delay csb = 50% to r l = 50 ? v out = 0.9 v bat , v bat = 16 v - - 20 s t doff turn-off delay csb = 50% to r l = 50 ? v out = 0.1 v bat , v bat = 16 v - - 20 s dv on/dt turn-on voltage slew-rate 90% to 30% of v bat ; r l = 50 ? ; v bat = 16 v 0.7 2.1 3.5 v/s dv off/dt turn-off voltage slew-rate 30% to 90% of v bat ; r l = 50 ? ; v bat = 16 v 0.7 2.1 3.5 v/s dv off clamp/dt turn-off voltage clamp slew- rate 30% to 80% of v out clamp r l = 500 ? 0.7 2.1 5.5 v/s serial diagnostic link (load capacitor at so = 200 pf) f sclk clock frequency 50% duty cycle 3 - - mhz t clh minimum time sclk = high - 160 - - ns t cll minimum time sclk = low - 160 - - ns t pcld propagation delay sclk to data at so valid 4.9 v ? v dd ? 5.1 v - - 100 ns t csdv csb = low to data at so active - - - 100 ns t sclch sclk low before csb low setup time sclk to csb change h/l 100 - - ns t hclcl sclk change l/h after csb = low setup time csb to sclk change l/h 100 - - ns t scld si input setup time sclk change h/l after si data valid 20 - - ns table 5. electrical ch aracteristics (continued) symbol parameter test condition min. typ. max. unit
docid7791 rev 7 11/19 l9823 electrical specifications 18 figure 3. output control register structure t hcld si input hold time si data hold after sclk change h/l --20ns t sclcl sclk low before csb high - 150 - - ns t hclch sclk high after csb high - 15, - - ns t pchdz csb l/h to output data float - - - 100 ns t reset minimum reset time reset = low - - - 160 ns table 5. electrical ch aracteristics (continued) symbol parameter test condition min. typ. max. unit table 6. outputs control description value si-bit 0 1 output on off 1 1 1 1 1 1 1 1 -3" ,3" #ontrol bitoutput #ontrol bitoutput #ontrol bitoutput #ontrol bitout put #ontrol bitoutput #ontrol bitoutput #ontrol bitout put #ontrol bitoutput '!0'03
electrical specifications l9823 12/19 docid7791 rev 7 2.4 power outputs characteristics for flyback current, outputs short circuit protection and diagnostics for output currents flowing into the circuit th e output voltages are limited. the typical value of this voltage is 50v. this function allows that the flyback current of a inductive load recirculates into the circuit; the fl yback energy is abso rbed in the chip. output short circuit protection sfpd = low (dedicated for loads without inrush current): when the output current exceeds the short ci rcuit threshold, the corresponding output overload latch is set after a delay time t dly scb and the output is switched off. the delay timer is started after each rise of csb and valid datas are transferred to the output control register. if the short takes place after the delay time has elapsed the shutdown is immediate (within 15 s). output short circuit protecti on sfpd = high (dedicated for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regul ation mode. the output current is determined by the output characteristics and the output voltage depends on the load resistance. in this mode high power is dissipated in the output transistor a nd its temperature increases rapidly. when the power transistor temperature exceeds the therma l shutdown threshold, the overload latch is set and the corresponding output switched off. for the load diagnostic in output off condition each output features a diagnostic current sink, of typ 60 a.
docid7791 rev 7 13/19 l9823 functional description 18 3 functional description 3.1 general the l9823 integrated circuit features 8 power low-side-driver outputs. data is transmitted to the device using the serial peripheral interface = spi protocol. the power outputs features voltage clamping function for flyback current recirculation and are protected against short circuit to vbat. the diagnostics recognizes two outputs faul t conditions: 1) overcurrent and thermal overload in switch-on condition and 2) open load or short to gnd in switch-off condition for all outputs. the outputs status can be read out via the serial interface. the chip internal reset is a or function of the external reset signal and internally generated undervoltage reset signal. 3.2 output stages control each output is controlled with its latch and with a common reset line, which enables all outputs. the control data are transmitted via the si input, th e timing of the serial interface is shown in figure 4 . the device is selected with low csb signal and the input data are transferred into the 8 bit shift register at every falling sclk edge. the rising edge of the csb latches the new data from the shift register to the drivers. figure 4. timing of the serial interface the spi register data are transferred to the outp ut latch at rising csb edge. the digital filter between csb and the output latch ensures that the data are transferred only after 8 sclk cycles or multiple of 8 sclk cycles since th e last csb falling edge. the csb changes only at low sclk. #3" 3#,+ 3) 3/ tsclch thclcl tclh tcll tsclcl thclch tcs dv tpcld tpchdz notdefined $ $ tscl d th cld $ $ $ '!0'03
functional description l9823 14/19 docid7791 rev 7 3.3 diagnostics the output voltage at all outputs is compar ed with the diagnostic threshold, typ 0,55 ? v dd = v dg . fault condition 1 output short circuit to vbat: ? for sfpd = low the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. the diagnostic bit is high. ? for sfpd = high the output was switched on and the voltage at the output exceeds the diagnostics threshold. the output operat es in current regulation mode or has been switched off due to thermal shutdown. the status bit is high. fault condition 2 open load or output short circuit to gnd: ? the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic current source, the load is interrupted. the diagnostic bit is low. ? at the falling edge of csb the output status data are transf erred to the shift register. when scb is low, data bits contained in the shift register are transferred to so output at every rising sclk edge. figure 5. pulse diagram to read the outputs status register table 7. diagnostic for outputs output output voltage status bit output mode off > dg-threshold high correct operation off < dg-threshold low fault condition 2) on < dg-threshold low correct operation on > dg-threshold high fault condition 1) '!0'03 #3" 3#,+ 3) 3/ -3" ,3" -3" ,3"
docid7791 rev 7 15/19 l9823 functional description 18 figure 6. structure of the outputs status register '!0'03 'ldj 'ldj 'ldj 'ldj 'ldj 'ldj 'ldj 'ldj 06% /6% 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw 'ldjqrvwlfelwrxwsxw
applications information l9823 16/19 docid7791 rev 7 4 applications information the typical application diagram for parallel input spi control is shown in figure 7 . figure 7. typical application circ uit diagram for the l9823 circuit. for higher current driving capab ility more outputs of the same ki nd can be paralleled. in this case the maximum flyback ener gy should not exceed the limit value for single output. the immunity of the circuit with respect to the transients at the output is verified during the characterization for test pulses 1, 2 and 3a , 3b, din40839 or iso7637 part 3. the test pulses are coupled to the outputs with 200pf se ries capacitor. the correct function of the circuit with the test pulses coupled to the outp uts is verified during the characterization for the typical application with r = 16 ? to 200 ? , l= 0 to 600mh loads. all outputs withstand test pulses without damage. '!0'03 #3" 3#,+ 3) 3/ 2eset "!4 6 2,loads ?0 6/,4 !'% 2%'5,!4 /2 $$ 6 $iag 1 #3" 3) 3#,+ 3/ /54 /5 4 /5 4 /54 /54 /5 4 /54 /54 '.$ $iag $i ag 2eset 1 #( /4 $iag 1 1 1 $i ag 1 #( #( #( #( $iag 1 $iag 1 $iag 1 1 #( $iag 2eset 3hift2egister /utput,atch 30) )n terface 2eset 5ndervoltage 2%3%4 1 1 1 1 1 1 $iag $iag $iag $iag $iag $iag ) /, /v er 4e mperature $etect 'ate #ontrol /, #( #( 3&0$ 6 $' $iag 6 $$ ) 3#" , ,
docid7791 rev 7 17/19 l9823 package information 18 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 8. so24 mechanical data and package dimensions '!0'03 /54,).%!.$ -%#(!.)#!,$!4! $)- mm inch -). 490 -!8 -). 490 -!8 ! ! " # $ % e ( h , k ?plq?pd[ ddd h$vdimensiondoesnotincludemoldflashprotusionsorga te burrs-oldflashprotusionsorgateburrsshallnotexceed mmperside 3/ # 7eight gr
revision history l9823 18/19 docid7791 rev 7 6 revision history table 8. document revision history date revision changes 16-apr-2003 4 initial release. 13-apr-2011 5 document reformatted. added new order code in table 1: device summary on page 1 . 17-jun-2013 6 updated: figure 3: output control re gister structure on page 11 and figure 6: structure of the outputs status register on page 15 . 19-sep-2013 7 updated disclaimer.
docid7791 rev 7 19/19 l9823 19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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